1. Field of the Invention
The present invention relates to a signal phase calibration method. More particularly, the present invention relates to a signal phase calibration circuit and a display driver with a built-in-phase-calibration circuit.
2. Description of Related Art
Signal offsets may occur due to factors such as fabrication process, environment, signal transmission path, and etc., and therefore cause a setup time problem and a hold time problem. FIG. 1A is a diagram illustrating a signal path. FIG. 1B is a timing diagram of the signals of FIG. 1A. A signal source (a transmitter 110) transmits the signals (clock CLK10 and data D10) to a receiver 130 via a signal path 120. Therefore, the receiver 130 may output a corresponding clock CLK11 and a data D11 to a secondary circuit (not shown) according to the received clock CLK10 and the data D10.
The clock CLK11 and the data D11 may have signal offsets during transmission. In FIG. 1B, signal offsets occur such that the transition of the data D11 is close to the rising edge of the clock CLK11. Thus a set-up time problem is caused because the rising edge of the clock CLK11 appears within the required setup time for the transition of the data D11, and the data D11 would be erroneously sampled by the secondary circuit (not shown) based on the rising edge of the clock CLK11. Moreover, a hold time problem may be caused if the hold time of the clock CLK11 after the rising edge is not long enough.
FIG. 2A is a block diagram illustrating a conventional system that uses delay buffer for modifying signal offsets. FIG. 2B is a timing diagram of the signals of FIG. 2A. The delay buffer 240 with a fixed delay time may be applied to delay the clock CLK11, so as to generate a clock CLK12 for eliminating the signal offsets. However, the fixed delay buffer cannot flexibly modify the offsets of the digital signals along with a fabrication process variation and a voltage variation etc.